PCB Stackup Design Guide: 2-Layer vs 4-Layer, Via Types, and Impedance Control

The stackup is one of the first decisions in a PCB design and one of the hardest to change later. It determines how many routing layers you have, whether you can achieve controlled impedance, how well the board handles return currents, and which via types are available to you. Choosing the wrong stackup early means either redesigning it before fabrication or accepting compromises that affect signal integrity, EMC performance, and manufacturability throughout the life of the product.

This article covers the practical decision points: when a 2-layer board is sufficient, when it is not, how to choose a 4-layer stackup, what impedance control requires, and how via type selection affects your options when routing fine-pitch devices including 0.4 mm pitch BGAs.

Two-layer boards: when they work

A 2-layer board has copper on the top and bottom surfaces only. There are no inner layers, no dedicated ground plane, and no power plane. All signals, power, and ground routing must fit on two layers.

Two-layer boards are cheaper and faster to fabricate than multilayer boards, and for the right type of design they are entirely appropriate. They work well when:

• Clock speeds are low, generally below 10 MHz, and edge rates are not particularly fast
• There are no high-current switching nodes or switching regulators with fast rise times
• No controlled impedance traces are required (USB, LVDS, Ethernet, RF)
• The design does not need to meet strict EMC conducted or radiated emissions limits
• Component density is low enough that routing on two layers is practical without excessive compromise

Simple sensor interfaces, motor drivers with low switching frequencies, LED controllers, and similar designs are often well-served by two layers. The cost saving is real, particularly for prototypes and low-volume production runs.

The limitation of a 2-layer board is the lack of a solid, dedicated ground plane. Instead of a continuous copper reference beneath every signal trace, the ground network is a set of routed traces and copper pours. Return currents cannot follow directly beneath signal traces; they take whatever path is available through the ground network, which typically means longer paths and larger current loops. This is the primary reason 2-layer boards are harder to pass EMC testing and more prone to signal integrity problems at higher speeds.

When to move to four layers

Four layers are worth the additional cost whenever any of the following apply:

• Clock frequencies above 10 MHz or fast edge rates. Fast switching signals create significant return current, and a ground plane is the only reliable way to keep those return currents contained beneath the signal traces.
• Switching regulators on the board. A DC-DC converter's switching node is a continuous source of high-frequency energy. Without a ground plane to constrain the return currents, that energy couples into adjacent circuits and out of the board as radiated emissions.
• Controlled impedance signals. USB, LVDS, Ethernet, CAN, RF traces, and high-speed DDR or SERDES interfaces all require a specific trace impedance, typically 50 ohms single-ended or 90 to 100 ohms differential. Achieving controlled impedance requires a known dielectric thickness between the signal layer and the reference plane, which only exists when you have a dedicated reference plane in the stackup.
• Products requiring CE or FCC certification. EMC compliance depends heavily on stackup. A 2-layer board without a ground plane will almost always require significant filtering and shielding to pass conducted and radiated emissions tests. A 4-layer board with a solid ground plane dramatically reduces the filtering burden.
• BGA devices, especially fine-pitch. BGAs with a pitch of 0.8 mm or below benefit significantly from inner layers for fanout. At 0.5 mm pitch and below, inner layers are typically required.

Standard 4-layer stackups

The most common 4-layer stackup assigns the layers as follows:

• Layer 1 (top): Signal and components
• Layer 2: Ground plane (GND)
• Layer 3: Power plane (PWR) or second signal layer
• Layer 4 (bottom): Signal and components

This arrangement gives every signal layer an immediately adjacent ground reference layer. Layer 1 signals reference the ground plane on layer 2, and layer 4 signals reference the power plane on layer 3. The power plane itself references ground through the dielectric between layers 2 and 3, which provides distributed inter-plane capacitance across the entire board area. This is not a substitute for local decoupling capacitors, but it does contribute to overall power supply stability.

An alternative arrangement often seen in designs where routing space on layer 4 is more important than power plane coverage is Signal / Ground / Signal / Ground, using both inner layers as reference planes and routing power as a distributed network of wide traces on the outer layers. This gives better EMC performance at the cost of a dedicated power plane. For most digital designs, the first arrangement (Signal / Ground / Power / Signal) is the better default choice.

For designs with higher layer counts, 6 or 8 layers, the same principle applies: every signal layer should be adjacent to a reference plane (ground or power). Burying signal layers between two reference planes provides shielding that further reduces radiated emissions and crosstalk.

Impedance control

Controlled impedance means the characteristic impedance of a trace is specified and manufactured to a defined tolerance. The characteristic impedance of a PCB trace depends on four things: trace width, trace thickness, dielectric thickness between the trace and its reference plane, and the dielectric constant (Dk or Er) of the substrate material.

To achieve controlled impedance on a 4-layer board, you need to specify the target impedance to your manufacturer and they will adjust trace width (or confirm that your specified width achieves the target) based on their actual stackup parameters. This is why using a manufacturer's standard stackup is important: if you design to a stackup that the manufacturer does not build, the dielectric thicknesses will differ from your simulation, and the impedance will be off.

Common impedance targets:

• 50 ohms single-ended: RF, coaxial-referenced traces, general high-speed single-ended signals
• 90 ohms differential: USB 2.0 data lines (D+ and D-)
• 100 ohms differential: LVDS, Ethernet, USB 3.0, CAN

Most manufacturers provide a stackup calculator or a document listing the trace widths required for standard impedance targets on their standard 4-layer stackup. Eurocircuits and PCBway both publish stackup data for their standard builds. Use those values when designing your traces, and specify controlled impedance on your fabrication notes so the manufacturer verifies the result with a TDR measurement on a test coupon.

Via types

A via is a drilled and plated hole that provides an electrical connection between layers. Not all vias are the same: they differ in which layers they connect, how they are manufactured, and what they cost. Choosing the right via type for each part of your design affects both routing density and board cost.

Through-hole vias

The standard via type drilled through all layers of the board, from top to bottom. Through-hole vias are produced by mechanical drilling and are the cheapest and most reliable option. They are the default choice for any signal or power connection that does not need to be on an outer layer only. The limitation is that a through-hole via occupies space on all layers, even layers where it carries no signal, which reduces routing space on inner layers and can create routing congestion in dense areas of the design.

Typical minimum drill sizes for through-hole vias in standard manufacturing:

• Eurocircuits standard: 0.20 mm drill, 0.45 mm pad (0.125 mm annular ring minimum)
• PCBway standard: 0.20 mm drill, 0.45 mm pad (0.125 mm annular ring minimum)

Blind vias

A blind via connects an outer layer to one or more inner layers but does not pass through the entire board. A blind via starting on the top layer, for example, might connect layer 1 to layer 2 without reaching layer 3 or layer 4. The via is visible from the top surface but not from the bottom: it is "blind" from one end.

Blind vias are more expensive than through-hole vias because they require controlled-depth drilling or laser drilling and additional process steps. They are used when through-hole vias would consume too much routing space on layers where the via carries no signal, or when the pitch of a device is too tight to route using only through-hole vias. The most common use case is BGA fanout.

Buried vias

A buried via connects inner layers only. It is not visible from either outer surface. Buried vias are the most expensive via type: they require drilling a partial stackup before lamination, then laminating additional layers over the buried via structure. They appear in high-density designs with 6 or more layers where inner layer routing density is extremely constrained. For most 4-layer designs, buried vias are not necessary and their cost is rarely justified.

Microvias

Microvias are very small vias produced by laser drilling rather than mechanical drilling. They connect adjacent layers only and have a drill diameter typically in the range of 0.075 to 0.10 mm. Microvias are the basis of HDI (high-density interconnect) PCB technology. They are used in smartphones, high-density SoC designs, and any application where via size must be minimised to accommodate fine-pitch BGAs or extremely dense component placement. HDI fabrication is significantly more expensive than standard multilayer fabrication and involves a different manufacturing process.

Via-in-pad and fine-pitch BGA fanout

As BGA pitch decreases, conventional through-hole via fanout becomes impossible or impractical. At 1.0 mm pitch, there is room to route traces between BGA pads and place a via nearby. At 0.8 mm pitch, routing between pads requires tight trace widths and careful planning. At 0.5 mm pitch, through-hole vias may just fit with one via between rows of pads. At 0.4 mm pitch, there is no space between pads for a via at all. The only option is to place the via directly inside the BGA pad itself: via-in-pad.

Via-in-pad

A via-in-pad places the via drill hole at the centre of the SMD pad. During assembly, the via provides a direct connection from the BGA ball down to inner layers without requiring any trace routing away from the pad first. This is the only practical fanout approach for 0.4 mm pitch BGAs and is commonly used at 0.5 mm pitch as well.

Via-in-pad has a critical manufacturing requirement: the via must be filled and capped. If the via hole is left open, solder will wick down into the via barrel during reflow, starving the joint of solder and causing an incomplete or open connection. The industry-standard solution is to fill the via with conductive or non-conductive epoxy, then plate copper over the fill so the pad surface is flat and solderable. This is specified as "via-in-pad, filled and capped" or "VIPPO" (via in pad plated over) in fabrication notes. It adds cost, but it is not optional for 0.4 mm pitch BGA designs.

Blind vias for BGA fanout

For 0.4 mm and 0.5 mm pitch BGAs, using blind vias from layer 1 to layer 2 rather than through-hole vias provides two benefits. First, the via does not consume space on layer 3 or layer 4, freeing those layers for routing under the BGA footprint. Second, with a blind via-in-pad approach, the via connects to the adjacent ground or signal plane directly, keeping connection lengths short and inductance low, which matters for power pins and high-speed signals under the device.

The combination of via-in-pad and blind vias is standard practice for fine-pitch BGA fanout on 4-layer and 6-layer boards. The via is placed in the pad, connects from layer 1 to layer 2, and the signal or power routing continues on layer 2 outward from the BGA footprint. For high-density parts with many internal BGA rows, a mix of through-hole dog-bone vias at the outer rows and via-in-pad blind vias at the inner rows is also used depending on the pitch and available routing channels.

Annular rings: do not undersize them

The annular ring is the copper ring that surrounds a drilled via hole. Its width is the distance from the edge of the drill hole to the edge of the copper pad. If the annular ring is too small, drill registration tolerances can cause the hole to break out of the pad, leaving a partial or missing copper ring on one side. This is a reliability and manufacturing defect that either causes the board to be scrapped or, if it passes inspection, creates a mechanically weak via that is prone to failure under thermal cycling.

Manufacturers specify minimum annular ring values based on their drill registration tolerances. Using values at or below the minimum increases defect risk. Staying above the minimum gives the process margin.

Published minimum annular ring values for common manufacturers:

• Eurocircuits standard pool service: 0.15 mm minimum annular ring. Pad diameter must be at least drill diameter plus 0.30 mm, giving 0.15 mm of ring on each side. This applies to mechanically drilled through-hole and blind vias.
• Eurocircuits HDI / microvia service: 0.10 mm minimum annular ring for laser-drilled microvias. Eurocircuits supports microvia diameters from 0.075 mm upward on their HDI service tiers. Always verify against the PCB Visualizer design rule checker for your chosen service class, as the rules vary between their pool, proto, and HDI offerings.
• PCBway standard multilayer: 0.15 mm minimum annular ring for mechanically drilled through-hole vias.
• PCBway HDI / microvia: 0.075 mm minimum annular ring for laser-drilled microvias. PCBway's HDI service supports microvia drill diameters down to 0.10 mm with a 0.075 mm annular ring, making it suitable for 0.4 mm pitch BGA via-in-pad designs that fit within these constraints. Confirm the specific HDI tier and pad requirements on the PCBway capabilities page before finalising your padstack.

A practical rule for standard through-hole vias: use a pad diameter at least 0.35 to 0.40 mm larger than the drill diameter. For a common 0.30 mm drill, that means a 0.65 to 0.70 mm pad, giving a 0.175 to 0.20 mm annular ring on each side. This sits comfortably above the manufacturing minimum and gives the drill process room to work.

For blind vias and microvias, the annular ring rules are tighter and vary by manufacturer and process tier. Confirm the specific values with your manufacturer before designing your via padstack. Designing to the absolute minimum and then discovering the manufacturer requires a larger ring means either a stackup change or a waiver, neither of which is a position you want to be in before fabrication.

Specifying the stackup to your manufacturer

Your fabrication package should include a clear stackup specification. At minimum, this means:

• Layer count and layer assignments (which layers are signal, ground, power)
• Finished board thickness (typically 1.6 mm for standard designs)
• Copper weight per layer (1 oz / 35 µm is standard for signal layers; 2 oz for power layers carrying significant current)
• Controlled impedance traces: which layers, what target impedance, what trace width you have used
• Via types used: through-hole only, or blind/buried vias required
• Via-in-pad with filling and capping if applicable
• Surface finish (HASL, ENIG, immersion silver): ENIG is required for fine-pitch BGAs and any via-in-pad design

Both Eurocircuits and PCBway provide online tools that let you specify these parameters and get a real-time cost and design rule check before ordering. Using their standard stackup definitions rather than a custom stackup keeps cost down and ensures their published design rules apply without modification.

If your design involves controlled impedance, fine-pitch BGAs, or any HDI via technology, consider sending the design for a layout review before submitting for fabrication. Stackup and via errors are among the most expensive to discover after the order is placed. Our PCB layout review covers stackup selection, via design, annular ring compliance, and manufacturability as core review items.