Layout errors are visible. You can see a trace too thin, a pad too small, a via in the wrong place. Schematic errors are invisible until you power up — and by then, you have a board in your hand that does not work.
The most common failures we see: wrong decoupling values, missing pull-ups on open-drain outputs, voltage regulators without the correct feedback network, ESD protection on the wrong pins, power domains that sequence incorrectly.
None of these are exotic. All of them are caught in a schematic review.
No TVS or series resistor. A transient on the bus will destroy U1 (FTDI). Add PRTR5V0U2X or equivalent ESD protection.
The MCU datasheet requires 1V8 core to come up before the 3V3 IO domain. Current sequencing violates this. Add a delay RC or use a dedicated sequencer.
10kΩ pull-ups will limit rise time to ~3µs at 10pF bus capacitance. For Fast mode, use 2.2kΩ to 4.7kΩ.
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