10 Common PCB Schematic Mistakes

Schematic errors are the most expensive mistakes in PCB development. They are invisible in Gerber review, they survive DRC, and they often do not show up until a board is powered on the bench, or worse, until a production unit fails in the field. These are the ten mistakes we find most consistently in the designs we review, ranked roughly by the severity of the consequences.

1. Reset and mode-select pins left floating

Many microcontrollers have an active-low RESET pin, a BOOT0 pin, or similar mode-selection inputs. Without a defined logic state, these pins pick up noise, power-on transients, or charge from adjacent traces and cause unpredictable behaviour, the device may fail to start, reset mid-operation, or boot into a programming mode rather than normal firmware execution.

The fix is straightforward: add a 10 k pull-up or pull-down resistor as appropriate for the pin's active state, and add a 100 nF ceramic capacitor to ground in parallel with the resistor for noise immunity. If manual reset is required for programming or debugging, add a normally-open push button that pulls the pin to its active state when pressed.

2. Footprint does not match the component datasheet

Schematic symbols and PCB footprints frequently come from different sources, a symbol from a library, a footprint from an online repository, or one borrowed from a previous design. These are rarely checked against the actual component datasheet, and the mismatches can be subtle.

The areas most likely to have errors are:

• QFN variants: the exposed pad (EP) dimensions and thermal slug size differ significantly between package variants from different manufacturers, even when the overall outline is the same. An EP that is too large can cause solder bridging; one that is too small undermines thermal and electrical performance.
• Electrolytic capacitors: polarity markers and the relationship between the positive lead and the footprint's pin 1 are not standardised across footprint libraries. A reversed electrolytic is a very common failure mode on first-spin boards.
• SOT-23 variants: the 3-pin SOT-23 is used for transistors, MOSFETs, voltage regulators, and logic devices, and the pin assignments (gate/drain/source, or base/collector/emitter, or input/output/enable) vary by device family. A footprint taken from a transistor will have the wrong pin mapping for a regulator, even though the package outline is identical.

The correct practice is to verify pad pitch, pad dimensions, pin 1 location, and polarity markers against the component's own datasheet package drawing for every new component in a design. This is tedious but non-negotiable.

3. Decoupling capacitor placed on the wrong side of a ferrite bead

Ferrite beads are commonly used to filter high-frequency noise between a main supply rail (VCC_MAIN) and a sensitive or noisy sub-circuit (VCC_IC). The bead acts as a frequency-selective impedance, low impedance at DC and power frequencies, high impedance at the noise frequencies you want to suppress.

The decoupling capacitor must be placed on the IC side of the bead: between the bead output and the IC power pin. If the capacitor is placed on the main rail side, it does not see the noise that the IC sees. The bead's filtering effect is neutralised because the capacitor is not in the right position in the circuit to absorb the high-frequency noise that passes through to the IC.

This error is extremely common and easy to miss on a schematic because the net names and the visual layout of the page can obscure which side of the bead each component is on. Always trace the path explicitly: connector → bead → capacitor → IC pin. The capacitor belongs between the bead and the IC, not between the source and the bead.

4. Open-drain interrupt pin without a pull-up resistor

Many ICs signal an interrupt condition to the host MCU through an open-drain output: the pin can pull low, but it cannot drive high. It relies entirely on an external pull-up resistor to return the line to the inactive state. Without that resistor, the interrupt line floats when the IC releases it, and the MCU's input sees neither a clean high nor a clean low.

This is a very consistent finding in the designs we review. The interrupt pin is wired to a GPIO, the GPIO is configured as an input in firmware, and the system appears to work in basic testing because the PCB's parasitic capacitance or the MCU's weak internal pull-up happens to hold the line high. Under different conditions, temperature, or PCB population, the line floats into the undefined region and generates false interrupts or misses real ones.

The fix is a 4.7 k to 10 k pull-up resistor from the interrupt line to the appropriate logic supply voltage. Check the datasheet for the IC's VOL specification and the maximum sink current to confirm the resistor value keeps the low-level voltage within spec. Also confirm the logic supply voltage matches the MCU's input high threshold; a 5 V pull-up on a 3.3 V-tolerant input is a separate problem worth catching at the same time.

5. Crystal oscillator load capacitor values wrong

Crystal load capacitors are one of the most frequently misspecified passive components in embedded designs. The relationship between the schematic capacitor values and the crystal's rated load capacitance C_L is:

C_{L_sch} = (C1 × C2) / (C1 + C2) + C_stray

This must equal the crystal's rated C_L from the datasheet. For a symmetric design where C1 = C2 = C, this simplifies to C/2 + C_stray. The stray capacitance C_stray: the combined effect of the MCU's internal load capacitance on the crystal pins, the PCB trace capacitance, and the pad capacitance, is typically 2–5 pF for a well-routed design.

The consequences of wrong load capacitor values are serious: the oscillator may fail to start reliably at low temperature or low voltage, or it may start but run at the wrong frequency. Frequency error directly affects baud rate accuracy, timer precision, and RF carrier frequency in wireless designs. This is one of the most common mistakes we see and one of the hardest to diagnose after fabrication, because the oscillator often works fine at room temperature and only fails at the extremes of the operating range.

6. ESD protection missing on off-board interfaces

Any connector that leaves the PCB, USB, RS-485, CAN bus, Ethernet, external UART headers, sensor interfaces, is an ESD entry point. A human hand touching an unpowered cable, a connector mated while the board is running, or a cable routed near an ESD event can inject kilowatts of instantaneous power into unprotected signal lines.

Minimum protection for off-board interfaces is a TVS diode array on each signal line. The TVS clamps the transient voltage before it reaches the IC. Layout is equally important: the protection components must be placed between the connector and the IC: physically as close to the connector as possible, so that the transient energy is absorbed before it travels along the trace to the IC's ESD structures, which are not designed to handle energy at this level.

Common interfaces that are frequently left unprotected in the designs we see: UART breakout headers (treated as "just for debug"), I2C buses that leave the board to reach remote sensors, and RS-485 lines in industrial equipment where ESD events are a regular occurrence.

7. Power sequencing not considered

Many ICs with multiple supply rails require those rails to power up in a specific order. FPGAs almost universally have sequencing requirements, core voltage before I/O voltage is the typical constraint, but the specific order and timing varies by device family and manufacturer. Multi-core SoCs, DDR memory interfaces, and many power management ICs also specify sequencing in their datasheets.

Violating power sequencing requirements can cause the device to latch up and draw excessive current, fail to initialise, or in severe cases, suffer permanent damage from reverse biasing of internal protection diodes. The failure mode is often intermittent and temperature-dependent, making it difficult to diagnose without knowing to look for it.

For every IC in the design that has more than one supply pin, check the datasheet for a power sequencing section or a power-on reset timing diagram. If sequencing is required, confirm that the power architecture enforces it, either through the natural rise-time characteristics of the supply rails, through an explicit sequencing IC, or through enable pin control from a supervisory circuit.

8. IC reference design not followed

Every IC datasheet includes a typical application circuit or reference design: a recommended power supply topology, a specific network on the feedback pin, required bypass capacitors on particular pins, a gate resistor on a power switch, or a specific input filter. These circuits are not suggestions. They represent the operating conditions under which the IC was characterised, tested, and specified.

A common failure pattern: a designer uses the IC but omits or replaces parts of the reference circuit to save components, simplify the BOM, or work around a part availability issue. The IC then operates outside its characterised conditions. Startup behaviour changes, stability margins narrow, and the performance shown in the datasheet graphs no longer applies.

If the reference design is not available in the datasheet, or the datasheet is a preliminary or engineering sample version without an application section, that is also a risk to flag. It often means the evaluation of the component was incomplete at the time the part was selected, and the design is built on incomplete characterisation data.

9. IC power dissipation not verified

It is straightforward to calculate whether an IC will overheat, but it is frequently skipped. The calculation requires three values from the datasheet: the maximum power dissipation P_D, the junction-to-ambient thermal resistance θ_JA, and the maximum junction temperature T_J(max). The expected junction temperature is: T_J = T_ambient + (P_dissipated × θ_JA).

For linear regulators this is especially important. An LDO dropping 5 V to 3.3 V at 500 mA dissipates 850 mW as heat. In a SOT-23 package with a typical θ_JA of 250 °C/W, that is a junction temperature rise of 212 °C above ambient. At 25 °C ambient, the junction temperature exceeds 235 °C, far above the maximum rating of most devices. The schematic is technically correct, the part number is valid, the voltage is right, but the IC will fail under normal operating conditions.

For every linear regulator, power switch, gate driver, and high-current path in the design: calculate the expected power dissipation across the full operating range, confirm it is within the package limit, and confirm the PCB copper area or heatsink can handle the thermal load. For switching regulators, verify the efficiency across the expected load range and check that the worst-case dissipation stays within the package rating at maximum ambient temperature.

10. MOSFET not fully enhanced by the gate drive voltage

A standard MOSFET selected from a datasheet may list a gate threshold voltage V_GS(th) of "2 to 4 V typical." That range means the MOSFET begins to conduct somewhere in that window, not that it is fully enhanced. Full enhancement, meaning the on-resistance R_DS(on) from the datasheet, is typically achieved at V_GS = 10 V.

When this MOSFET is driven from a 3.3 V GPIO, the gate voltage is never enough to reach the fully-enhanced region. The MOSFET operates partially in its linear region, with a much higher R_DS(on) than the datasheet value, causing it to dissipate significantly more power than expected. Under load, the MOSFET heats up, threshold voltage shifts, and the situation worsens.

The fix is to use a logic-level MOSFET, which is characterised at V_GS = 4.5 V or lower, and to confirm the R_DS(on) specification is given at your actual drive voltage. If a standard MOSFET is required for other reasons, a gate driver or level-shifter is needed between the MCU GPIO and the gate.

What a second pair of eyes catches

The mistakes above share a common characteristic: they are easy to introduce and easy to miss in self-review. When you have been working on a schematic for weeks, you stop seeing it the way a fresh reviewer sees it. You know what the design is supposed to do, and your brain fills in the gaps.

A structured design review by someone who did not build the schematic covers exactly these failure modes systematically, from a checklist built on real manufacturing and debugging experience. If you have a board in progress and want to catch these issues before committing to fabrication, our schematic review service is designed for exactly this point in the design process.