EMC compliance failures are among the most expensive problems to fix late in a product development cycle. A failed pre-compliance test means engineering time, board respins, and compressed schedules, and if the failure is discovered in a third-party test house rather than in-house, the cost is compounded by re-testing fees and delays to market.

Most EMC issues are rooted in decisions made during schematic capture and PCB layout, not in the test chamber. The test chamber reveals the consequences of earlier decisions; it does not fix them. This article covers the design practices that give you the best chance of passing pre-compliance on the first attempt, applied at the point when they are cheapest: during design.

Start with a solid ground plane

A complete, unbroken ground plane on an inner layer is the single most important EMC measure in a PCB design. Everything else in this article works better when the ground plane is solid, and most of it fails without one.

The reason is return current. When a signal switches, the return current flows back to the source through the path of least inductance, which, for a trace over a ground plane, is directly under the signal trace on the adjacent ground layer. This keeps the current loop small. A small loop radiates very little energy at the frequencies where EMC standards apply.

If the ground plane is broken, by a slot, a cutout, a connector footprint with a large clearance, or a plane split, the return current cannot flow under the signal trace. It takes the next lowest-inductance path available, which is a longer route around the obstruction. The current loop area increases, and the radiated emissions increase with it. This is a direct cause of emissions failures.

Do not split the ground plane. The practice of separating analog and digital ground, once common in mixed-signal design guidelines, is now understood to cause more problems than it solves in the majority of designs. A split ground plane forces return currents to cross at the single connection point between the splits, creating a radiating current loop at exactly the location where you do not want one. Use a single ground plane with careful placement of noisy and sensitive circuits instead.

Power input filtering for mains-connected designs

If your design connects to the mains supply, the power entry point is your primary conducted emissions boundary. Switching power converters generate significant high-frequency noise on the supply lines, and without a properly designed input filter, that noise conducts back into the mains network, which is exactly what conducted emissions testing measures.

A mains entry filter should include:

  • Common-mode choke at the mains entry point, before the AC-DC converter. The common-mode choke presents high impedance to common-mode noise, current that flows on both L and N in the same direction, while passing the differential mains current with low impedance.
  • X-capacitors across L and N, rated 250 VAC minimum. These suppress differential-mode noise by providing a low-impedance path for noise that appears between L and N.
  • Y-capacitors from L to PE and from N to PE, using Y2-class safety-rated capacitors at minimum. These suppress common-mode noise by providing a return path to protective earth.

The filter must be placed before the AC-DC converter: between the mains connector and the converter input. A converter without an input filter is a conducted emissions problem in waiting. Budget AC-DC modules often omit or significantly undersize the input filter. Always verify the module's input filter design against the reference circuit in the datasheet, and supplement it on your board if necessary.

Decoupling strategy

Every IC power pin needs a decoupling capacitor. This is not new advice, but the execution details determine whether the capacitors actually work.

The standard value is 100 nF ceramic in an 0402 or 0603 package. The placement rule is: as close to the power pin as possible, on the same layer as the IC. The effectiveness of a decoupling capacitor decreases with distance from the pin, the series inductance of the trace between the capacitor and the pin reduces the capacitor's effectiveness at high frequencies, which is precisely the frequency range where decoupling matters for EMC.

The via to ground is equally important. Place it adjacent to the capacitor, immediately next to the capacitor pad, rather than at the far end of a trace. A long trace from the capacitor to the via adds inductance that degrades the decoupling effect.

In addition to per-pin decoupling, provide bulk capacitance at the supply rail entry point, typically 10–100 µF per rail, depending on the load transient requirements. Bulk capacitors handle lower-frequency transients that small ceramic capacitors cannot source. The combination of bulk capacitance at the rail entry and local 100 nF ceramics at each IC covers the frequency range relevant to both EMC and supply integrity.

The capacitor value matters less than placement. A 100 nF capacitor placed 20 mm from the power pin, which is common in poorly reviewed layouts, does almost nothing for high-frequency decoupling. A 47 nF capacitor placed immediately next to the pin is significantly more effective.

High-speed signal routing

High-speed signals are the primary source of radiated emissions in digital designs. The switching node of a DC-DC converter, clock distribution lines, USB data lines, and fast digital interfaces all generate energy at frequencies relevant to EMC standards.

The fundamental objective is to keep current loops small. A high-speed signal creates a current loop between the signal trace and its return path on the ground plane. The area of this loop determines how efficiently it radiates energy. Practices that keep the loop area small:

  • Route high-speed traces directly, avoid unnecessary length, bends, and detours that increase loop area
  • Keep the ground plane continuous beneath high-speed traces, any break in the plane forces the return current to take a longer path, increasing the loop area
  • Avoid routing high-speed signals across plane splits, slots, or via clearance areas where the return path is interrupted
  • When high-speed signals must change layers, place a ground via immediately adjacent to the signal via so the return path can transition layers at the same location

For differential pairs (USB, LVDS, Ethernet, CAN, RS-485), route both signals of the pair together with equal length and consistent spacing. The differential signal's return current flows in the opposite conductor of the pair, keeping the two conductors close together keeps the current loop small and the pair self-cancelling for radiated emissions.

Series termination on fast signal lines

Unterminated fast signal lines reflect at the far end and ring. The ringing extends the duration of the switching edge and generates energy at the ringing frequency, which is often in the range where EMC standards apply. A series resistor at the source end of the line damps the ringing by reducing the edge rate and absorbing reflected energy.

A 22–47 ohm series resistor placed as close as possible to the driving pin is the standard approach. The resistor and the line's characteristic impedance form a voltage divider, the initial launched wave is half the logic swing, which propagates to the load, reflects, and adds to arrive at the full logic level without ringing. The result is a slower, cleaner edge with significantly less high-frequency energy.

This technique is particularly effective for SPI lines running over long PCB traces, clock distribution lines, and any signal that exits the PCB via a cable, where cable emissions are a major EMC concern. The resistor value should be tuned to match the sum of the source impedance and the resistor to the line's characteristic impedance, for most PCB traces, values between 22 and 47 ohms are a good starting point.

Connector and interface filtering

Every off-board connector is a potential path for conducted and radiated emissions to exit the board and for external interference to enter it. Filtering at the connector is the most effective point to apply it, before signals reach the interior of the board where they can couple to other circuits.

For each off-board connector:

  • TVS diode arrays on data lines for ESD protection and transient suppression
  • Common-mode chokes on differential interfaces, CAN, RS-485, Ethernet, to suppress common-mode noise that cables pick up from the environment
  • Series resistors or ferrite beads on single-ended signal lines to limit edge rate and reduce high-frequency energy on the cable
  • Filter capacitors to ground on signal lines for low-pass filtering

Layout at the connector area is as important as component selection. Keep the unfiltered side of the connector (the board interior) physically separated from the filtered side (the connector pins). One approach is to use a ground plane slot across the connector area with a single connection point, the slot prevents noise from the board interior from coupling around the filter to the connector pins. Protection components sit between the connector pins and the slot; all other board circuitry connects on the other side of the slot.

Crystal and oscillator circuits

Crystal oscillator circuits are a consistent EMC offender. They generate a clean, stable, high-amplitude periodic signal, exactly the kind of signal that creates discrete spectral peaks in an emissions scan. The oscillator frequency and its harmonics appear as sharp spikes in the test data, and if any harmonic falls in a regulated frequency band, it becomes a compliance concern.

EMC-conscious crystal layout practices:

  • Keep crystal traces short: under 10 mm from MCU crystal pins to the crystal and load capacitors. Long traces increase the antenna area.
  • Do not route other signals under or over the crystal area on adjacent layers. Signals crossing the crystal area couple to the oscillator loop.
  • Add a ground ring around the crystal, its load capacitors, and the traces between them. The ground ring provides a local reference and shields the oscillator from surrounding signals.
  • Add a series resistor (typically 0–100 ohm, see the MCU datasheet for recommendations) on the crystal output line. This limits the edge rate of the clock signal as it propagates from the oscillator section, which reduces harmonics.
  • Place the crystal close to the MCU pins, the longer the traces, the more they radiate. The crystal circuit should be one of the most compact areas on the board.

PCB stackup

The stackup determines the impedance of traces, the proximity of signal layers to their return planes, and the overall effectiveness of the ground plane as an EMC measure. A well-chosen stackup is a foundation that all the other EMC practices build on.

For most designs, a 4-layer stackup of Signal / Ground / Power / Signal is the minimum recommended configuration for EMC-sensitive products. This arrangement gives each signal layer an adjacent ground reference layer, which keeps return current loops small and provides a ground plane reference for impedance-controlled routing. The power plane on layer 3 is referenced to the ground plane on layer 2, the thin dielectric between them forms a distributed decoupling capacitance across the entire board area.

Use an even layer count, 4, 6, 8, for manufacturing symmetry. Asymmetric stackups (an odd number of layers with an unbalanced arrangement of copper planes) can bow during lamination. Specify tight dielectric spacing between signal layers and their adjacent ground reference layers; close coupling reduces loop inductance and improves signal integrity and EMC performance simultaneously.

Applying these practices consistently

EMC design is largely a set of practices applied consistently across every area of the design, not a single technique applied in one place. The designs that fail pre-compliance typically have most of the practices right, but miss one or two in a specific area: a connector that was left unfiltered, a plane that was split to accommodate a layout constraint, or a crystal that was placed too close to an edge connector.

Most pre-compliance failures we see in submitted designs trace back to a small set of root causes: missing mains input filtering, a split or broken ground plane, and unfiltered off-board connectors. Getting these three areas right during design catches the majority of EMC issues before they reach the test chamber. If you want a structured review of your design's EMC practices before committing to fabrication, our PCB design review service includes EMC assessment as a core part of the layout review.